1. Field of the Invention
The present invention relates to a data signal line driving circuit for continuously sampling input signals and outputting them, and an image display apparatus which adopts the data signal line driving circuit.
2. Description of the Related Art
Hereinafter, a liquid crystal display apparatus and a data line driving circuit used therein will be described using conventional examples of an image display apparatus and a data signal line driving circuit.
An active matrix type liquid crystal display apparatus is well known. This apparatus is composed of a pixel array ARRAY, a scanning signal line driving circuit GD, and a data signal line driving circuit SD, as shown in FIG. 17.
The pixel array ARY includes scanning signal lines GL and data signal lines SL crossing the scanning signal lines GL. Each pixel PIX is provided in a matrix in each portion surrounded by two adjacent scanning signal lines GL and two adjacent data signal lines SL.
The data signal line driving circuit SD sequentially samples input video signals DAT in synchronization with a timing signal such as a clock signal CLKs, and amplifies each sampled video signal, if required, to output it to each data signal line SL.
The scanning signal line driving circuit GD sequentially selects each scanning signal line GL in synchronization with a timing signal such as a clock signal CLKg, and controls opening and closing of each switching element in each pixel PIX along the selected scanning signal line GL, there by writing each video signal (data) output to each data signal line SL into each pixel PIX and allowing data written into each pixel PIX to be held.
As shown in FIG. 18, each pixel PIX shown in FIG. 17 is composed of a field effect transistor SW which is a switching element and a pixel capacitance made of a liquid crystal capacitance CL and an auxiliary capacitance CS which is added if required.
As shown in FIG. 18, the data signal line SL is connected to one of electrodes of the pixel capacitance through a drain and a source of the transistor SW. A gate of the transistor SW is connected to the scanning signal electrode line GL, and the other electrode of the pixel capacitance is connected to a common electrode line of all the pixels. Due to a voltage applied to each liquid crystal capacitance CL, a transmittance or a reflectivity of liquid crystal is modulated, which contributes to a display.
Next, a method for sampling a video signal and outputting it to a data signal line will be described.
Examples of a method for driving a data signal line includes a dot sequential driving method and a line sequential driving method. Herein, only a dot sequential driving method will be described with reference to FIGS. 19 and 20. This description is also applicable to a line sequential driving method.
In each circuit shown in FIGS. 19 and 20, a shift register SR sequentially outputs sampling pulses while shifting them, in synchronization with a clock signal CLK (corresponding to the clock signal CLKs in FIG. 17). Sampling pulses N1, N2, N3, and N4 sequentially output from the shift register SR are sequentially supplied to respective analog switches G1, G2, G3, and G4. The analog switches G1, G2, G3, and G4 sequentially open in response to the respective sampling pulses N1, N2, N3, and N4, sequentially sampling video signals transmitted to a video signal line DAT, and sequentially outputting respective sampled video signals SL1, SL2, SL3, and SL4.
In the shift register SR, unit circuits as shown in FIG. 21 or 22 are arranged.
The unit circuit shown in FIG. 21 forms the shift register SR which shifts pulses only in one direction, and is composed of two clock control inverter circuits 201 and one inverter circuit 202.
The unit circuit shown in FIG. 22 forms the shift register SR which shifts pulses in both directions, and is composed of two clock control inverter circuits 201 and two inverter circuits 203.
Both the shift registers SR have a structure of a half-latch circuit, which latches a pulse only in one direction of a rising or falling of a clock signal and outputs a pulse width in one period of the clock signal.
In an example shown in FIG. 19, outputs of the shift register SR are directly used as the sampling pulses N1 to N4. Therefore, the continuous sampling pulses overlap each other by a half as shown in FIG. 23.
In an example shown in FIG. 20, respective overlapped portions of adjacent output pulses of the shift register SR are used as the sampling pulses N1 to N4. Therefore, the continuous sampling pulses do not overlap each other as shown in FIG. 24.
FIG. 25 shows an exemplary scanning signal line driving circuit. In this circuit, as shown in FIG. 27, a shift register SR sequentially outputs sampling pulses N1 to N4 while shifting them, in synchronization with a clock signal CLK corresponding to the clock signal CLKg in FIG. 17. This driving circuit is designed in such a manner that adjacent output pulses of the shift register SR do not overlap each other. Furthermore, by selecting an overlapped portion between the signal thus obtained and a pulse width control signal GPS from outside, each sampling pulse having a desired pulse width is obtained.
In the conventional data signal line driving circuits shown in FIGS. 19 and 20, every other sampling pulse, N1 to N4, partially overlaps with one another as shown in FIG. 23, and the continuous sampling pulses, N1 to N4, partially overlap each other as shown in FIG. 24. This is because, in the conventional circuit configuration, a sampling pulse rises when another sampling pulse falls. Furthermore, due to variation and the like in transistor characteristics in the circuit, a timing of a part of sampling pulses may be shifted. In this case, an overlapped portion of the respective sampling pulses becomes larger.
In the case where sampling pulses overlap each other, a level of a video signal to be written into a data signal line may be changed. For example, in the circuit shown in FIG. 20, when the subsequent sampling pulse N3 rises before the sampling pulse N2 is turned off as shown in FIG. 26, the video signal DAT is drawn to the data signal line SL3 corresponding to the sampling pulse N3 as well as the data signal line SL2 corresponding to the sampling pulse N2. Therefore, a level of the video signal DAT to be output to the data signal line SL2 decreases by xcex94 V. Similarly, when the sampling pulse N4 rises before the sampling pulse N2 is turned off in the circuit shown in FIG. 19, the video signal DAT is drawn to two data signal lines SL2 and SL4. Therefore, a level of the video signal DAT to be output to the data signal line SL2 decreases.
Consequently, a desired pixel potential cannot be obtained, making it difficult to obtain a normal display. In particular, when there is a variation in an overlapped portion of sampling pulses, level change values of a video signal and a pixel potential vary, which may cause roughness and a stripe pattern in an image.
The circuit shown in FIG. 25 has the following disadvantage: although a pulse width of each sampling pulse is adjusted, it is required to generate and supply the pulse width control signal GPS having a frequency twice that of the clock signal CLK; therefore, a burden on an external circuit is increased.
A data signal line driving circuit is provided, which sequentially forms a plurality of sampling signals and continuously samples input signals to output such input signals, in response to the plurality of sampling signals, wherein the sampling signals respectively represent sampling periods thereof which are different from each other, and a pulse width of each of the sampling signals is prescribed to be small so that rising and falling of each of the sampling signals do not overlap each other.
In one embodiment of the present invention, each of the sampling signals is obtained as a NAND signal or a NOR signal between a pulse signal and a signal obtained by delaying the pulse signal through a plurality of inverter circuits, whereby a pulse width of each of the sampling signals is prescribed to be small.
In another embodiment of the present invention, a capacitance is connected between the plurality of inverter circuits.
In another embodiment of the present invention, a capacitance is connected between each of the inverter circuits and either a NAND circuit or a NOR circuit.
In another embodiment of the present invention, a pulse signal is a pulse output from a shift register.
In another embodiment of the present invention, the above-mentioned data signal line driving circuit includes a shift register capable of shifting sampling pulses in both directions or in one direction, wherein each of the sampling signals is obtained by using either a NAND signal or a NOR signal between two adjacent output pulses output from the shift register, and a delay signal of the NAND signal or the NOR signal, whereby the sampling signal of either the NAND signal or the NOR signal, having a decreased pulse width, is obtained.
In another embodiment of the present invention, the above-mentioned data signal line driving circuit includes a shift register capable of shifting sampling pulses in one direction, wherein each of the sampling signals is obtained as either a NAND signal or a NOR signal between one of two adjacent output pulses output from the shift register and the other pulse which is delayed, whereby a pulse width of each of the sampling signals is decreased.
In another embodiment of the present invention, a time of the delay is about 10 nsec to about 100 nsec.
According to another aspect of the present invention, an active matrix type image display apparatus includes: a plurality of data signal lines arranged in a column direction: a plurality of scanning signal lines arranged in a row direction; a plurality of pixels arranged in a matrix surrounded by the data signal lines and the scanning signal lines; a data signal line driving circuit for supplying video data to the data signal lines; and a scanning signal line driving circuit for supplying a scanning signal to the scanning signal lines, wherein the data signal line driving circuit is a data signal line driving circuit which sequentially forms a plurality of sampling signals and continuously sampling input signals to output them, in response to the sampling signals, wherein the sampling signals respectively represent sampling periods thereof which are different from each other, and a pulse width of each of the sampling signals is prescribed to be small so that rising and falling of each of the sampling signals do not overlap each other.
In one embodiment of the present invention, the scanning signal line driving circuit and the data signal line driving circuit are formed on the same substrate with the pixels.
In another embodiment of the present invention, active elements included in the scanning signal line driving circuit, the data signal line driving circuit, and the pixels are polycrystalline silicon thin film transistors.
In another embodiment of the present invention, the active elements are formed on a glass substrate by a process at about 600xc2x0 C. or lower.
Hereinafter, the function of the present invention will be described.
In the data signal line driving circuit of the present invention, a pulse width of each sampling signal is prescribed to be small so that the rising and falling of each sampling signal for sampling a video data signal do not overlap each other. In this structure, after a video signal is output to a data signal line, a video signal is output to the subsequent signal line. Thus, a video signal on a data signal line can be prevented from being drawn to another data signal line, and a video signal at a desired voltage level can be output to any data signal line.
In one embodiment, a NAND or a NOR between a pulse signal delayed by a plurality of inverter circuits and a pulse signal which is not delayed is obtained. In this structure, a pulse width of each sampling signal can be prescribed to be small without using a control signal from outside. Thus, a video signal at a desired voltage level can be written to a data signal line without burdening an external control circuit or the like.
In another embodiment, a capacitance is added between the inverter circuits, or between the inverter circuit and a circuit for obtaining either a NAND signal or a NOR signal. In this structure, by appropriately selecting a value of the above-mentioned capacitance, a pulse width can be controlled. Thus, a pulse width can be arbitrarily set so as not allow sampling pulses to overlap each other. Because of this, after a video signal is output to a data signal line, a video signal is output to the subsequent data signal line. This prevents a video signal on a data signal line from being drawn to another data signal line, and a video signal at a desired voltage level can be written to a data signal line.
In another embodiment, a pulse signal is an output signal from a shift register. In this structure, a sampling pulse is obtained by using two adjacent output pulses output from the shift register. These sampling pulses overlap each other by about a half, but every other sampling pulse does not overlap with one another (i.e., a sampling pulse falls completely, and then, a sampling pulse after the subsequent sampling pulse rises). Thus, a video signal on a data signal line is prevented from being drawn to another data signal line, and a video signal at a desired voltage level can be written to a data signal line.
In another embodiment, a shift register is capable of shifting sampling pulses in both directions, and by using a NAND signal (or a NOR signal) between two adjacent output pulses output from the shift register, and a delay signal thereof, a pulse width of the NAND signal (or the NOR signal) is prescribed to be small. In this structure, after a sampling pulse falls completely, the subsequent sampling pulse rises, so that adjacent sampling pulses do not overlap each other. Therefore, a video signal on a data signal line is prevented from being drawn to another data signal line, and a video signal at a desired voltage level can be written to a data signal line. Furthermore, adjacent sampling pulses do not overlap each other, so that only one data signal line is connected to a video signal line at a time during driving. Thus, a capacitance load on a video signal line can be decreased compared with that in the above-mentioned structure, and the burden on an external video signal source can be alleviated and writing performance of a data signal line driving circuit itself can be enhanced. This structure is applicable to a shift register capable of shifting sampling pulses only in one direction.
In another embodiment, a shift register is capable of shifting sampling pulses in one direction, and by generating a NAND signal (or a NOR signal) between one of two adjacent output pulses output from the shift register and a delay signal of the other output pulse, a pulse width of the NAND signal (or a NOR signal) is prescribed to be small. In this structure, after a sampling pulse falls completely, the subsequent sampling pulse rises in the same way as in the above-mentioned structure. Therefore, fluctuation of a video signal (which is caused when the video signal is drawn to the subsequent data signal line) does not affect the previous data signal line, and a video signal at a desired voltage level can be written to a data signal line.
Furthermore, in the same way as in the aforementioned structure, adjacent sampling pulses do not overlap each other. Therefore, only one data signal line is connected to a video signal line at a time during driving. Thus, a capacitance load on a video signal line can be decreased, compared with that of the above-mentioned structure. This can alleviate a burden on an external video signal source and enhance driving ability of a data signal line driving circuit itself.
Furthermore, compared with the above-mentioned structure, a circuit which generates a NAND signal (or a NOR signal) between two adjacent output pulses output from the shift register is eliminated. Thus, in the case where a scanning direction of the shift register is limited to one direction, circuit configuration can be simplified, and miniaturization of a driving circuit, reduction in a production cost, and enhancement of a production yield can be expected.
In another embodiment, the time of a delay is about 10 nsec to about 100 nsec.
A timing shift of sampling pulses caused by rising characteristics of sampling pulses and a variation in transistor characteristics are on the order of about 10 nsec. Therefore, by setting the delay time at about 10 to about 50 nsec and decreasing the sampling pulse width, fluctuation of a video signal (which is caused when the video signal is drawn to the subsequent data signal line) does not affect the previous data signal line, making it possible to write a video signal at a desired voltage level to a data signal line.
Furthermore, the image display apparatus of the present invention is provided with the above-mentioned data signal line driving circuit.
Thus, as described above, in the data signal line driving circuit, fluctuation of a video signal (which is caused when the video signal is drawn to the subsequent data signal line) does not affect the previous data signal line, and a video signal at a desired voltage level can be written to a data signal line. Therefore, a video signal at a desired voltage level can also be written to a display electrode, and an image with high display quality can be displayed.
In one embodiment, the scanning signal line driving circuit and the data signal line driving circuit are formed on the same substrate with the pixels. In this structure, the pixels for performing a display, the data signal line driving circuit and the scanning signal line driving circuit for driving the pixels can be produced on the same substrate during the same step. Therefore, the production cost and mounting cost can be reduced, and the ratio of mounting satisfactory products can be enhanced.
In another embodiment, at least the pixels and the data signal line driving circuit are disposed on a polycrystalline silicon thin film formed on an insulating substrate.
When transistors are formed of polycrystalline silicon thin films as described above, high characteristics of driving force can be obtained, compared with the case of amorphous silicon thin film transistors used in a conventional active matrix liquid crystal display apparatus. Therefore, the pixels and the signal line driving circuit can easily be formed on the same substrate.
In another embodiment, the active elements are formed on a glass substrate by a process at about 600xc2x0 C. or lower.
As described above, in the case where polycrystalline silicon thin film transistors are produced at about 600xc2x0 C. or lower, it is possible to use an inexpensive glass substrate which has a low strain temperature but permits the apparatus to be large. Therefore, a large image display apparatus can be produced at a low cost.
Thus, the invention described herein makes possible the advantages of: (1) providing a data signal line driving circuit which is capable of enhancing display quality in an image display apparatus by preventing sampling pulses from overlapping each other; and (2) providing an image display apparatus which adopts the data signal line driving circuit.
These and other advantages of the present invention will become apparent to those skilled in the art upon reading and understanding the following detailed description with reference to the accompanying figures.